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INTEGRATED CIRCUITS
DATA SHEET
TDA4663T Baseband delay line
Product specification Supersedes data of September 1993 File under Integrated Circuits, IC02 1996 Nov 22
Philips Semiconductors
Product specification
Baseband delay line
FEATURES * Two delay lines, using the switched-capacitor technique, for a delay time of one horizontal line (1H) minus 55 ns (64 s - 55 ns) * Adjustment-free application * Handles negative or positive colour-difference input signals * Clamping of AC-coupled input signals [mostly colour-difference signals (R-Y) and (B-Y)] * VCO without external components * 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 s line) * Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal * Output buffer amplifiers. QUICK REFERENCE DATA SYMBOL VP1 VP2 IP(tot) Vi(p-p) PARAMETER analog supply voltage (pin 9) digital supply voltage (pin 1) total supply current input signal PAL/NTSC (peak-to-peak value) (R-Y); pin 16 (B-Y); pin 14 Gv Vo gain ----- of colour-difference output signals for PAL and NTSC Vi V 11 -------V 16 V 12 -------V 14 ORDERING INFORMATION TYPE NUMBER TDA4663T PACKAGE NAME SO16 DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm -1 -1 0 - - 1.3 1.3 MIN. 4.75 4.75 - 5 5 5.9 TYP. GENERAL DESCRIPTION
TDA4663T
The TDA4663T is an integrated baseband delay line circuit with a delay time of one horizontal line (1H) minus 55 ns (64 s - 55 ns).
MAX. 5.25 5.25 7.0 - - V V
UNIT
mA V V
+1
dB
0
+1
dB
VERSION SOT109-1
1996 Nov 22
2
1996 Nov 22
clamping pulse 7 11 (R-Y)
BLOCK DIAGRAM
Philips Semiconductors
Baseband delay line
handbook, full pagewidth
(R-Y) LP
16 LINE MEMORY SAMPLEAND-HOLD
SIGNAL CLAMPING
mostly colour-difference input signals pre-amplifiers output buffers 12
mostly colour-difference output signals
(B-Y) LP
14 LINE MEMORY SAMPLEAND-HOLD
SIGNAL CLAMPING
(B-Y)
3
3 MHz shifting clock DIVIDER BY-192
VP1 FREQUENCY PHASE DETECTOR LP digital supply 1 GND2 VP2 6 MHz CCO DIVIDER BY-2
9
analog supply
TDA4663T
sandcastle pulse input
5
SANDCASTLE DETECTOR
2 6 13 15
n.c. n.c. n.c. n.c.
10
3
4, 8
MED800
GND1
Product specification
TDA4663T
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Baseband delay line
PINNING SYMBOL VP2 n.c. GND2 i.c. SAND n.c. VCL i.c. VP1 GND1 Vo(R-Y) Vo(B-Y) n.c. Vi(B-Y) n.c. Vi(R-Y) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION supply voltage for digital part (+5 V) not connected ground for digital part (0 V) internally connected sandcastle pulse input not connected clamping pulse input internally connected supply voltage for analog part (+5 V) ground for analog part (0 V) (R-Y) output signal (B-Y) output signal not connected (B-Y) input signal not connected (R-Y) input signal
i.c. 4
handbook, halfpage
TDA4663T
VP2 1 n.c. 2 GND2 3
16 Vi(R-Y) 15 n.c. 14 Vi(B-Y) 13 n.c.
TDA4663T
SAND 5 n.c. 6 VCL 7 i.c. 8
MED801
12 Vo(B-Y) 11 Vo(R-Y) 10 GND1 9 VP1
Fig.2 Pin configuration.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together. SYMBOL VP1 VP2 V5 Vn In Tstg Tamb Ptot Ves Note 1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 220 UNIT K/W PARAMETER supply voltage (pin 9) supply voltage (pin 1) voltage on pin 5 voltage on pins 7, 11, 12, 14 and 16 current on pins 7, 11 and 12 storage temperature operating ambient temperature total power dissipation electrostatic handling for all pins note 1 CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 - -25 -20 - - +7 +7 VP + 1.0 VP 20 +150 +70 100 500 MAX. V V V V mA C C mW V UNIT
1996 Nov 22
4
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
CHARACTERISTICS VP = 5.0 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz; Tamb = 25 C; measurements taken in Fig.3; unless otherwise specified. SYMBOL VP1 VP2 IP1 IP2 Vi(p-p) PARAMETER analog supply voltage (pin 9) digital supply voltage (pin 1) supply current supply current input signal (peak-to-peak value) pin 16 pin 14 Vi(max)(p-p) maximum symmetrical input signal (peak-to-peak value) pin 16 pin 14 I14, 16 R14, 16 C14, 16 V14, 16 Vo(p-p) input leakage current (during picture content) input resistance during clamping input capacitance input clamping voltage output signal (peak-to-peak value) pin 11 pin 12 V11/V12 V11, 12 R11, 12 Gv ratio of output amplitudes at equal input signals DC output voltage output resistance Vo voltage gain ----Vi noise voltage (RMS value; pins 11 and 12) weighted signal-to-noise ratio (pins 11 and 12) jitter of output signal to external sandcastle reference V5 crosstalk between channels crosstalk between channels Vi14, 16 = 0 V; note 1 Vo = 1 V (p-p); note 1 - - Vi14, 16 = 665 mV (p-p) -0.4 proportional to VP 2.5 - -1 - - - V14 = 0 V; RS = 300 ; 30 V11 = 1.35 V (p-p) V16 = 0 V; RS = 300 ; 30 V12 = 1.35 V (p-p) 1.3 1.3 0 2.9 300 0 - 54 - - - - - - +0.4 3.3 400 +1 V V dB V dB proportional to VP before clipping before clipping 1.6 1.6 0.06 - - 1.3 - - 0.085 - - 1.5 - - 0.1 40 10 1.7 V V A k pF V - - 1.3 1.3 - - V V CONDITIONS MIN. 4.75 4.75 - - 5 5 5.1 0.8 TYP. MAX. 5.25 5.25 5.9 1.1 UNIT V V mA mA
Colour-difference input signals
Colour-difference output signals
Vn(rms) S/N(W) tj ct(11, 12) ct(12, 11) ct(14, 12)
1.2 - 20 - - -
mV dB ns dB dB dB
crosstalk direct from input to output V16 = 0 V; RS = 300 ; 30 signal V14 = 1.35 V (p-p)
1996 Nov 22
5
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
SYMBOL ct(16, 11) SVRR
PARAMETER
CONDITIONS
MIN. - -
TYP. - -
MAX.
UNIT dB dB
crosstalk direct from input to output V14 = 0 V; RS = 300 ; 30 signal V16 = 1.35 V (p-p) supply voltage ripple rejection V11, 12/VR clamping offset during H-clamp (peak-to-peak value) unwanted signals (line-locked) (peak-to-peak value) residual clock (3 MHz) meander needles VR = 100 mV (p-p); fR = 10 Hz to 1 kHz; V11, 12 = 1.35 V (p-p) V14 = V16 = 0 V; RS = 300 V14 = V16 = 0 V; active video; RS = 300 34
V11, 12(p-p) V11, 12(p-p)
-
-
5
mV
- - -
- - - 63.555 - 0.055 15.625 - 2.5 - - - - VP - 0.1 +0.1 - - 2 - -
6.25 1.5 2.5 63.555 + 0.015 17.0 VP + 1.0 - V5 - 0.5 10 10 1
mV mV mV s
td
line delay time
for PAL signals for NTSC signals
64 - 0.125 64 - 0.055 64 + 0.015 s 63.555 - 0.125 14.2
Sandcastle pulse input (pin 5) fBK V5 tBK Vslice Ii Ci tli Vclamp Ii Ci tclamp tr tf Notes 1. Noise voltage at f = 10 kHz to 1 MHz; RS < 300 . 2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing. burst-key frequency/sandcastle frequency top pulse voltage top pulse duration internal slicing level input current input capacitance lock-in time for PLL note 2 kHz V s V A pF ms
4.0 - V5 - 1.0 - - - 3.5 -0.5 - - 0.1 10 10
Clamping pulse input (pin 7) clamping pulse ON clamping pulse OFF input current input capacitance clamping pulse duration rise time fall time VP +1.5 10 10 3 - - V V A pF s ns ns
1996 Nov 22
6
Philips Semiconductors
Product specification
Baseband delay line
APPLICATION INFORMATION
TDA4663T
handbook, full pagewidth
colourdifference signals Vi(R-Y) 1 nF Vi(B-Y) 16
TDA4663T
11 Vo(R-Y) Vo(B-Y)
LINE DELAY
14
LINE DELAY
12 4 8 7
1 nF
VCO 2 SSC (5 V) 5 LINE-LOCKED PLL / PULSE PROCESSING +5.1 V 9 +5.1 V 1
(1)
clamping pulse (CMOS) n.c. n.c. n.c. n.c.
6 13 15
10
(1)
3
100 nF 10 10 22 F
100 nF 560 5.1 V
MED802
+12 V
(1) Positioned close to pins.
Fig.3 Application circuit.
1996 Nov 22
7
Philips Semiconductors
Product specification
Baseband delay line
PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 3.9 mm
TDA4663T
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 0.24 0.23 L 1.05 0.041 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.0098 0.057 0.069 0.0039 0.049
0.019 0.0098 0.39 0.014 0.0075 0.38
0.028 0.004 0.012
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 91-08-13 95-01-23
1996 Nov 22
8
Philips Semiconductors
Product specification
Baseband delay line
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end.
TDA4663T
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Nov 22
9
Philips Semiconductors
Product specification
Baseband delay line
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA4663T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Nov 22
10
Philips Semiconductors
Product specification
Baseband delay line
NOTES
TDA4663T
1996 Nov 22
11
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/02/pp12
Date of release: 1996 Nov 22
Document order number:
9397 750 01375

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